Sorting non-volatile memories

ABSTRACT

A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.

BACKGROUND OF THE INVENTION

The present invention relates generally to manufacturing quality andmore particularly to manufacturing quality for electronic non-volatilerandom access memory devices such as flash memory chips, cards, andmodules.

Non-volatile random access memories (NVRAMS) such as flash memories aresubject to manufacturing defects as well as limited erase/program/readcycles. Detecting whether NVRAMS will fail early during their lifetimeat the time of manufacture is a challenge and results in increasedmanufacturing costs and the unnecessary rejection of many usabledevices.

SUMMARY

As disclosed herein, a computer-implemented method for sortingnon-volatile random access memories (NVRAMS) includes testing a failuremetric for each of a plurality of NVRAMS over a plurality of testingsessions to capture failure metric data that corresponds to theplurality of NVRAMS. The method also includes determining a trend in thefailure metric as a function of testing cycles for each of the pluralityof NVRAMS from the failure metric data, and separating the plurality ofNVRAMS into groups based on the trend in the failure metric as afunction of testing cycles. A corresponding computer program product andcomputer system are also disclosed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram depicting one example of an NVRAMpackage in accordance with at least one embodiment of the presentinvention;

FIG. 2 is a flowchart depicting one example of a NVRAM sorting method inaccordance with at least one embodiment of the present invention;

FIG. 3 is a workflow diagram depicting one example of a NVRAM testingenvironment in accordance with at least one embodiment of the presentinvention;

FIG. 4 is a graph depicting one example of failure metric data inaccordance with at least one embodiment of the present invention; and

FIG. 5 is a block diagram depicting one example of a computing apparatus(i.e., computer) suitable to, or adaptable to, executing the methodsdisclosed herein.

DETAILED DESCRIPTION

The embodiments disclosed herein recognize that the cost of exhaustivetesting on NVRAMS is prohibitive and may contribute to device wear. Theembodiments disclosed herein also recognize that the ability to predictfuture device failures may reduce the required testing burden at thetime of manufacture. Furthermore, the frequency and costs associatedwith unnecessary rejections and post-manufacturing failures may also bereduced.

It should be noted that references throughout this specification tofeatures, advantages, or similar language herein do not imply that allof the features and advantages that may be realized with the embodimentsdisclosed herein should be, or are in, any single embodiment of theinvention. Rather, language referring to the features and advantages isunderstood to mean that a specific feature, advantage, or characteristicdescribed in connection with an embodiment is included in at least oneembodiment of the present invention. Thus, discussion of the features,advantages, and similar language, throughout this specification may, butdo not necessarily, refer to the same embodiment.

Furthermore, the described features, advantages, and characteristics ofthe invention may be combined in any suitable manner in one or moreembodiments. One skilled in the relevant art will recognize that theinvention may be practiced without one or more of the specific featuresor advantages of a particular embodiment. In other instances, additionalfeatures and advantages may be recognized in certain embodiments thatmay not be present in all embodiments of the invention.

These features and advantages will become more fully apparent from thefollowing drawings, description and appended claims, or may be learnedby the practice of the invention as set forth hereinafter.

FIG. 1 is a schematic block diagram depicting one example of an NVRAMpackage 100 in accordance with at least one embodiment of the presentinvention. As depicted, the NVRAM package 100 includes a number of die110 that are stacked and interconnected with each other and with asubstrate 120. The depicted NVRAM package 100 also includes anencapsulant 130 that encapsulates and protects the NVRAM package 100.The depicted NVRAM package 100 also includes one or more interconnectionelements 140 that enable mounting the NVRAM package 100 on a circuitboard and interconnecting with other NVRAM packages 100 as well as othercircuits.

The NVRAM package 100 and other forms of NVRAM may be subject to memorywear degradations within the individual memory cells on the die 110 inaddition to packaging faults due to manufacturing issues. While many ofthe faults and some of the degradations may be easily detected withtesting at the time of manufacture, others may not become unacceptablefor a considerable length of time. Furthermore, some degradation or wearis expected and can be tolerated as long as the package can perform wellover an expected lifetime after which the NVRAM packages 100, or thecomponents or systems into which they are integrated, can be replaced asa whole.

The embodiments disclosed herein recognize that detecting degradationwithin individual NVRAM components within a computer storage system andreplacing those components increases the maintenance costs associatedwith computer storage. The embodiments disclosed herein also recognizethat the ability to predict, at the time of manufacture, NVRAMcomponents that are at high risk of failure in the field cansubstantially reduce those maintenance costs. The embodiments disclosedherein also recognize that detecting failure metric patterns or trendsmay improve the ability to assess which NVRAM components are at highrisk of failure in the field and/or reduce the number of testing cyclesneeded to achieve a sufficiently high level of confidence for theassessment.

FIG. 2 is a flowchart depicting one example of a NVRAM sorting method200 in accordance with at least one embodiment of the present invention.As depicted, the NVRAM sorting method 200 includes capturing (210)failure metric data, determining (220) whether a selected confidencelevel has been attained, determining (230) trends in the failure metricdata, separating (240) NVRAMS into groups, and scrapping or reworking(250) unacceptable groups. The NVRAM sorting method 200 enables thedetection of NVRAM components at the time of manufacture that have ahigh risk of failure in the field.

Capturing (210) failure metric data may include testing a failure metricfor each member of a set of NVRAMS over multiple testing sessions andthereby capture failure metric data that corresponds to the set ofNVRAMS. Examples of the failure metric include grown bad blocks, totalbad blocks, a bit error rate, and an error count. The multiple testingsessions may occur at the time of manufacture of the NVRAMS or thecomponents or systems into which they are integrated.

Determining (220) whether a selected confidence level has been attainedmay include determining whether enough data has been captured to achievethe selected confidence level. For example, determining (220) may assesswhether the number of testing sessions and the quantity of failuremetric data that has been collected is sufficient to determine the riskof field failures.

In some embodiments, statistical analysis is used to determine how manytesting sessions are required to determine the risk of failure in thefield of the NVRAMS. For example, one or more separation metrics may bederived from the failure metric data that enable separating the NVRAMSinto the groups. Statistical analysis may be used to determine theconfidence level of the separation metrics for the collected failuremetric data. In certain embodiments, the statistical analysis is dynamicand is updated with each testing session and may be dependent on theparticular failure metric pattern(s) for a specific NVRAM or NVRAMgroup. Consequently, the number of test cycles may be open ended untilthe selected confidence level is achieved for each NVRAM or NVRAM group.

Determining (230) trends in the failure data may include determining anexpected future value for the failure metric, or one or more parameterscorrelated thereto such as derivatives of the failure metric as afunction of usage. For example, curve fitting may be conducted on thefailure metric data as a function of usage so that an estimate of thefailure metric may be generated without conducting additional testingsessions.

Separating (240) the NVRAMS into groups based may include determiningwhether a trend in the failure metric for a particular NVRAM deviatessignificantly from typical trends in the failure metric for the NVRAMS.Separating (240) NVRAMS into groups may also include clustering failuremetric patterns using techniques known to those of skill in the art ofstatistical analysis or the like. For example, N failure metric valuesfor each NVRAM may be used to form data elements in an multi-dimensionalspace (e.g., vectors of N dimensions) and Euclidean distances or innerproducts may be used to determine groupings. Other examples includehierarchical clustering, k-means clustering and expectationmaximization. In some embodiments, the failure metric data is weightedaccording to the testing session. For example, more recent testingsession may be weighted higher than initial testing sessions. Separating(240) NVRAMS into groups may also include physically separating theNVRAMS according to the clustered groups. The separated groups may alsobe labeled (either automatically or via human assistance) to facilitaterouting of the groups to the next appropriate phase of manufacturing ordistribution. Examples of groups include a scrap group, a rework group,an acceptable quality group, and an exceptional quality group.

In some embodiments, an average, median, or centroid of the group iscompared with various thresholds or multidimensional space limits todetermine how the clustered group should be routed. In such anembodiment, some NVRAMS within a clustered group may be labeled androuted differently than if they were individually labeled and routed.The thresholds or limits used to separate the NVRAMS into groups may bedynamically adjusting as additional testing sessions are conducted.

In some embodiments, a separation metric is derived from the failuremetric data that enables separation into groups. For example, thecentroids of two cluster groups could be used to calculate a separationmetric that corresponds to a line that connects the centroids. Thedistributions of the separation metrics for the two groups can then beused to determine one or more thresholds that can be used to sort theNVRAMS into the two groups. The separation metrics and thresholds mayalso be applied to NVRAMS that are subsequently tested.

Scrapping or reworking (250) unacceptable groups may include routing theNVRAMS corresponding to unacceptable cluster groups to scrapping orreworking stations within a manufacturing environment. In someembodiments, the failure metric data is analyzed to determine faultydevice locations for NVRAMS within a reworking group. The identifiedfaulty device locations may facilitate effective rework of the NVRAMS.

FIG. 3 is a workflow diagram depicting one example of a NVRAM testingenvironment in accordance with at least one embodiment of the presentinvention. As depicted, various forms of NVRAMS 310 may be tested by atesting module 320 as directed by one or more test programs 330. TheNVRAMS 310 may be tested previous to, or after, packaging andintegration. Examples of the NVRAMS 310 include die, chips, wafers,modules, cards, and racks.

The test module 320 under direction of the test programs 330 may collectdata 340 that is used for various purposes 350 including failureprediction, dynamic adjustment of separation metrics and thresholds,process optimization, identification of fault locations and the like.

FIG. 4 is a graph depicting one example of failure metric data 400 inaccordance with at least one embodiment of the present invention. Asdepicted, the failure metric data 400 includes various failure metricpatterns 410 including acceptable patterns 410A and unacceptablepatterns 410B.

While conventional testing typically sorts NVRAMS based on an averagevalue of the failure metric for a specific number of testing cycles, theembodiments herein enable the detection of trends in the failure metricpatterns. Consequently, unacceptable NVRAMS may be detected with a fewernumber of testing cycles. For example, the derivative or predicted(i.e., extrapolated) future value of the failure metric for theunacceptable NVRAMS may exceed a selected threshold well before theaverage value—particularly at a selected level of confidence.Consequently, the unacceptable patterns 410B may be flagged with just afew testing cycles (e.g., 3 or 4 instead of 5 or 6).

FIG. 5 is a block diagram depicting one example of a computing apparatus(i.e., computer 500) suitable to, or adaptable to, executing the methodsdisclosed herein. It should be appreciated that FIG. 5 provides only anillustration of one embodiment and does not imply any limitations withregard to the environments in which different embodiments may beimplemented. Many modifications to the depicted environment may be made.

As depicted, the computer 500 includes communications fabric 502, whichprovides communications between computer processor(s) 505, memory 506,persistent storage 508, communications unit 512, and input/output (I/O)interface(s) 515. Communications fabric 502 can be implemented with anyarchitecture designed for passing data and/or control informationbetween processors (such as microprocessors, communications and networkprocessors, etc.), system memory, peripheral devices, and any otherhardware components within a system. For example, communications fabric502 can be implemented with one or more buses.

Memory 506 and persistent storage 508 are computer readable storagemedia. In the depicted embodiment, memory 506 includes random accessmemory (RAM) 516 and cache memory 518. In general, memory 506 caninclude any suitable volatile or non-volatile computer readable storagemedia.

One or more programs may be stored in persistent storage 508 forexecution by one or more of the respective computer processors 505 viaone or more memories of memory 506. The persistent storage 508 may be amagnetic hard disk drive, a solid state hard drive, a semiconductorstorage device, read-only memory (ROM), erasable programmable read-onlymemory (EPROM), flash memory, or any other computer readable storagemedia that is capable of storing program instructions or digitalinformation.

The media used by persistent storage 508 may also be removable. Forexample, a removable hard drive may be used for persistent storage 508.Other examples include optical and magnetic disks, thumb drives, andsmart cards that are inserted into a drive for transfer onto anothercomputer readable storage medium that is also part of persistent storage508.

Communications unit 512, in these examples, provides for communicationswith other data processing systems or devices. In these examples,communications unit 512 includes one or more network interface cards.Communications unit 512 may provide communications through the use ofeither or both physical and wireless communications links.

I/O interface(s) 515 allows for input and output of data with otherdevices that may be connected to computer 500. For example, I/Ointerface 515 may provide a connection to external devices 520 such as akeyboard, keypad, a touch screen, and/or some other suitable inputdevice. External devices 520 can also include portable computer readablestorage media such as, for example, thumb drives, portable optical ormagnetic disks, and memory cards.

Software and data used to practice embodiments of the present inventioncan be stored on such portable computer readable storage media and canbe loaded onto persistent storage 508 via I/O interface(s) 515. I/Ointerface(s) 515 may also connect to a display 522. Display 522 providesa mechanism to display data to a user and may be, for example, acomputer monitor.

One of skill in the art will appreciate that the above disclosedembodiments may be adapted for a variety of environments andapplications. Furthermore, the programs described herein are identifiedbased upon the application for which they are implemented in a specificembodiment of the invention. However, it should be appreciated that anyparticular program nomenclature herein is used merely for convenience,and thus the invention should not be limited to use solely in anyspecific application identified and/or implied by such nomenclature.

The embodiments disclosed herein include a system, a method, and/or acomputer program product. The computer program product may include acomputer readable storage medium (or media) having computer readableprogram instructions thereon for causing a processor to carry out themethods disclosed herein.

The computer readable storage medium can be a tangible device that canretain and store instructions for use by an instruction executiondevice. The computer readable storage medium may be, for example, but isnot limited to, an electronic storage device, a magnetic storage device,an optical storage device, an electromagnetic storage device, asemiconductor storage device, or any suitable combination of theforegoing. A non-exhaustive list of more specific examples of thecomputer readable storage medium includes the following: a portablecomputer diskette, a hard disk, a random access memory (RAM), aread-only memory (ROM), an erasable programmable read-only memory (EPROMor Flash memory), a static random access memory (SRAM), a portablecompact disc read-only memory (CD-ROM), a digital versatile disk (DVD),a memory stick, a floppy disk, a mechanically encoded device such aspunch-cards or raised structures in a groove having instructionsrecorded thereon, and any suitable combination of the foregoing. Acomputer readable storage medium, as used herein, is not to be construedas being transitory signals per se, such as radio waves or other freelypropagating electromagnetic waves, electromagnetic waves propagatingthrough a waveguide or other transmission media (e.g., light pulsespassing through a fiber-optic cable), or electrical signals transmittedthrough a wire.

Computer readable program instructions described herein can bedownloaded to respective computing/processing devices from a computerreadable storage medium or to an external computer or external storagedevice via a network, for example, the Internet, a local area network, awide area network and/or a wireless network. The network may comprisecopper transmission cables, optical transmission fibers, wirelesstransmission, routers, firewalls, switches, gateway computers and/oredge servers. A network adapter card or network interface in eachcomputing/processing device receives computer readable programinstructions from the network and forwards the computer readable programinstructions for storage in a computer readable storage medium withinthe respective computing/processing device.

Computer readable program instructions for carrying out operations ofthe present invention may be assembler instructions,instruction-set-architecture (ISA) instructions, machine instructions,machine dependent instructions, microcode, firmware instructions,state-setting data, or either source code or object code written in anycombination of one or more programming languages, including an objectoriented programming language such as Smalltalk, C++ or the like, andconventional procedural programming languages, such as the “C”programming language or similar programming languages. The computerreadable program instructions may execute entirely on the user'scomputer, partly on the user's computer, as a stand-alone softwarepackage, partly on the user's computer and partly on a remote computeror entirely on the remote computer or server. In the latter scenario,the remote computer may be connected to the user's computer through anytype of network, including a local area network (LAN) or a wide areanetwork (WAN), or the connection may be made to an external computer(for example, through the Internet using an Internet Service Provider).In some embodiments, electronic circuitry including, for example,programmable logic circuitry, field-programmable gate arrays (FPGA), orprogrammable logic arrays (PLA) may execute the computer readableprogram instructions by utilizing state information of the computerreadable program instructions to personalize the electronic circuitry,in order to perform aspects of the present invention.

Aspects of the present invention are described herein with reference toflowchart illustrations and/or block diagrams of methods, apparatus(systems), and computer program products according to embodiments of theinvention. It will be understood that each block of the flowchartillustrations and/or block diagrams, and combinations of blocks in theflowchart illustrations and/or block diagrams, can be implemented bycomputer readable program instructions.

These computer readable program instructions may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus to produce a machine, suchthat the instructions, which execute via the processor of the computeror other programmable data processing apparatus, create means forimplementing the functions/acts specified in the flowchart and/or blockdiagram block or blocks. These computer readable program instructionsmay also be stored in a computer readable storage medium that can directa computer, a programmable data processing apparatus, and/or otherdevices to function in a particular manner, such that the computerreadable storage medium having instructions stored therein comprises anarticle of manufacture including instructions which implement aspects ofthe function/act specified in the flowchart and/or block diagram blockor blocks.

The computer readable program instructions may also be loaded onto acomputer, other programmable data processing apparatus, or other deviceto cause a series of operational steps to be performed on the computer,other programmable apparatus or other device to produce a computerimplemented process, such that the instructions which execute on thecomputer, other programmable apparatus, or other device implement thefunctions/acts specified in the flowchart and/or block diagram block orblocks.

The flowcharts and block diagrams in the Figures illustrate thearchitecture, functionality, and operation of possible implementationsof systems, methods, and computer program products according to variousembodiments of the present invention. In this regard, each block in theflowchart or block diagrams may represent a module, segment, or portionof instructions, which comprises one or more executable instructions forimplementing the specified logical function(s). In some alternativeimplementations, the functions noted in the block may occur out of theorder noted in the figures. For example, two blocks shown in successionmay, in fact, be executed substantially concurrently, or the blocks maysometimes be executed in the reverse order, depending upon thefunctionality involved. It will also be noted that each block of theblock diagrams and/or flowchart illustration, and combinations of blocksin the block diagrams and/or flowchart illustration, can be implementedby special purpose hardware-based systems that perform the specifiedfunctions or acts or carry out combinations of special purpose hardwareand computer instructions.

It should be noted that this description is not intended to limit theinvention. On the contrary, the embodiments presented are intended tocover some of the alternatives, modifications, and equivalents, whichare included in the spirit and scope of the invention as defined by theappended claims. Further, in the detailed description of the disclosedembodiments, numerous specific details are set forth in order to providea comprehensive understanding of the claimed invention. However, oneskilled in the art would understand that various embodiments may bepracticed without such specific details.

Although the features and elements of the embodiments disclosed hereinare described in particular combinations, each feature or element can beused alone without the other features and elements of the embodiments orin various combinations with or without other features and elementsdisclosed herein.

This written description uses examples of the subject matter disclosedto enable any person skilled in the art to practice the same, includingmaking and using any devices or systems and performing any incorporatedmethods. The patentable scope of the subject matter is defined by theclaims, and may include other examples that occur to those skilled inthe art. Such other examples are intended to be within the scope of theclaims.

What is claimed is:
 1. A computer system comprising: one or moreprocessors; one or more computer readable storage media and programinstructions stored on the one or more computer readable storage media,the program instructions comprising instructions to execute a methodcomprising: testing, via the one or more processors, a plurality offlash memories to produce a failure metric for each of the plurality offlash memories over a plurality of testing sessions and thereby capturefailure metric data that corresponds to the plurality of flash memories;weighting, via the one or more processors, the failure metric dataaccording to the testing session; determining, via the one or moreprocessors, a trend in the failure metric as a function of testingcycles for each of the plurality of flash memories from the failuremetric data; repetitively conducting testing sessions, via the one ormore processors, until a selected confidence level is attained for thetrend in the failure metric as a function of testing cycles; clustering,via the one or more processors, the trends in the failure metric as afunction of testing cycles to provide a plurality of clustered groupsfor the failure metric data; physically separating, via the one or moreprocessors, the plurality of flash memories into routing groups androuting the routing groups via equipment controlled by the one or moreprocessors, according to the plurality of clustered groups; wherein thefailure metric comprises a grown bad blocks count; and wherein theplurality of clustered groups comprise a scrap or rework group, anacceptable quality group, and an exceptional quality group and routingthe routing groups comprises routing the scrap or rework group toscrapping station or reworking station within a manufacturingenvironment.